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ADP5070AREZ-R7 데이터시트(PDF) 28 Page - Analog Devices

부품명 ADP5070AREZ-R7
상세설명  Independent Positive and Negative Outputs
PDF  28 Pages
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ADP5070AREZ-R7 데이터시트(HTML) 28 Page - Analog Devices

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Data Sheet
ADP5070
Rev. A | Page 27 of 27
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.18
COMPLIANT
TO JEDEC STANDARDS MO-220-WGGD.
BOTTOM VIEW
TOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.75
2.60 SQ
2.35
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
15
16
5
Figure 52. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-8)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-153-ACT
20
11
10
1
EXPOSED
PAD
(Pins Up)
6.60
6.50
6.40
4.50
4.40
4.30
6.40
BSC
TOP
VIEW
BOTTOM VIEW
0.65 BSC
0.15
0.05
COPLANARITY
0.10
1.20 MAX
1.05
1.00
0.80
0.30
0.19
SEATING
PLANE
0.20
0.09
3.05
3.00
2.95
8°
0°
0.75
0.60
0.45
4.25
4.20
4.15
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 53. 20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]
(RE-20-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADP5070ACPZ
−40°C to +125°C
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
CP-20-8
ADP5070ACPZ-R7
−40°C to +125°C
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
CP-20-8
ADP5070AREZ
−40°C to +125°C
20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]
RE-20-1
ADP5070AREZ-R7
−40°C to +125°C
20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]
RE-20-1
ADP5070CP-EVALZ
Evaluation Board for the LFCSP_WQ
ADP5070RE-EVALZ
Evaluation Board for the TSSOP_EP
1
Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12068-0-6/15(A)



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