ADP5071ACPZ-R7 datasheet(17/28 Pages) AD

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ADP5071

Data Sheet

Rev. A | Page 16 of 27

To configure the simultaneous enable mode, connect the SEQ pin

to the VREG pin. Both regulators power up simultaneously

when the EN2 pin is taken high. The EN1 pin enable can be

used to enable the internal references ahead of enabling the

outputs, if desired. The simultaneous enable mode timing is

shown in Figure 42.

VIN

DISCONNECT

SWITCH TURN ON

VPOS

TIME

VNEG

SIMULTANEOUS ENABLE MODE

(SEQ = HIGH, EN2 = HIGH)

Figure 42. Simultaneous Enable Mode

To configure the sequential enable mode, pull the SEQ pin low.

In this mode, either VPOS or VNEG can be enabled first by using

the respective EN1 pin or EN2 pin. Keep the other pin low. The

secondary supply is enabled when the primary supply completes

soft start and its feedback voltage reaches approximately 85% of

the target value. The sequential enable mode timing is shown in

Figure 43.

DISCONNECT

SWITCH TURN ON

DISCONNECT

SWITCH TURN ON

TIME

VPOS

VNEG

VPOS

VNEG

1. VPOS FOLLOWED BY VNEG

(SEQ = LOW, EN1 = HIGH, EN2 = LOW)

2. VNEG FOLLOWED BY VPOS

(SEQ = LOW, EN2 = HIGH, EN1 = LOW)

SEQUENTIAL ENABLE MODE

VIN

Figure 43. Sequential Enable Mode

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