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ADP7157ACPZ-02-R7 데이터시트(PDF) 22 Page - Analog Devices |
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ADP7157ACPZ-02-R7 데이터시트(HTML) 22 Page - Analog Devices |
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22 / 24 page ![]() Data Sheet ADP7157 Rev. A | Page 21 of 23 PCB LAYOUT CONSIDERATIONS Place the input capacitor as close as possible to the VIN pin and ground. Place the output capacitor as close as possible to the VOUT pin and ground. Place the bypass capacitors (CREG, CREF, and CBYP) for VREG, VREF, and VBYP close to the respective pins (VREG, REF, and BYP) and ground. The use of a 0805, a 0603, or a 0402 size capacitor achieves the smallest possible footprint solution on boards where area is limited. Maximize the amount of ground metal for the exposed pad, and use as many vias as possible on the component side to improve thermal dissipation. Figure 63. Sample 10-Lead LFCSP PCB Layout Figure 64. Sample 8-Lead SOIC PCB Layout |
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