ML7204-003 datasheet(13/214 Pages) LAPIS

13 / 214 page

FEDL7204-003-02

ML7204-003

13/214

Timings of PDNB, XO, and AVREF

(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2

= 0.0 V, Ta = –20 to 60

C unless otherwise specified)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power-down signal pulse

width

tPDNB

PDNB pin

250

—

s

AVDD supply delay time

tAVDDON

—

Oscillation activation time

txtal

—

AVREF = 1.4 (90%)

C5 = 4.7

F, C6 = 0.1 F

(See Figure 9)

—

600

AVREF rise time

tAVREF

AVREF = 1.4 (90%)

C5 = 2.2

F, C6 = 0.1 F

(See Figure 9)

—

300

Figure 1 Timings of PDNB, XO, and AVREF

(Note)

The capacitance of the AVREF capacitor (C5) affects the AVREF rise time and analog characteristics. If

weight is given to the analog characteristics, specify 4.7

F, and if it is given to the AVREF rise time, specify

2.2

F. The electrical characteristics for the analog characteristics that are described above are guaranteed in

both capacitances.

PDNB

0 V

DVDD

tPDNB

DVDD

AVDD

0 V

DVDD

AVDD

VREGOUT

0 V

Approx.

2.5V

tAVDDON

AVREF

Approx.

1.4 V

0 V

AVDD

txtal

0 V

tAVREF

90%

DVDD AVDD

90%

ML7204-003 데이터시트(PDF) 13 Page - LAPIS Semiconductor Co., Ltd.

ML7204-003 데이터시트(HTML) 13 Page - LAPIS Semiconductor Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL