CLC1007 datasheet(18/27 Pages) EXAR

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exar.com/CLC1007

Rev 1D

CLC1007, CLC2007, CLC4007

Power Dissipation

Power dissipation should not be a factor when operating

under the stated 2kΩ load condition. However, applications

with low impedance, DC coupled loads should be analyzed

to ensure that maximum allowed junction temperature is

not exceeded. Guidelines listed below can be used to verify

that the particular application will not cause the device to

operate beyond it’s intended operating range.

Maximum power levels are set by the absolute maximum

junction rating of 170°C. To calculate the junction

temperature, the package thermal resistance value ThetaJA

(θJA) is used along with the total die power dissipation.

TJunction = TAmbient + (θJA × PD)

Where TAmbient is the temperature of the working

environment.

In order to determine PD, the power dissipated in the load

needs to be subtracted from the total power delivered by the

supplies.

PD = Psupply - Pload

Supply power is calculated by the standard power equation.

Psupply = Vsupply × IRMSsupply

Vsupply = VS+ - VS-

Power delivered to a purely resistive load is:

Pload = ((Vload)RMS2)/Rloadeff

The effective load resistor (Rloadeff) will need to include the

effect of the feedback network. For instance,

Rloadeff in Figure 3 would be calculated as:

RL || (Rf + Rg)

These measurements are basic and are relatively easy to

perform with standard lab equipment. For design purposes

however, prior knowledge of actual signal levels and load

impedance is needed to determine the dissipated power.

Here, PD can be found from

PD = PQuiescent + PDynamic - Pload

Quiescent power can be derived from the specified IS values

along with known supply voltage, Vsupply. Load power can

be calculated as above with the desired signal amplitudes

using:

(Vload)RMS = Vpeak / √2

( Iload)RMS = ( Vload)RMS / Rloadeff

The dynamic power is focused primarily within the output

stage driving the load. This value can be calculated as:

PDynamic = (VS+ - Vload)RMS × ( Iload)RMS

Assuming the load is referenced in the middle of the power

rails or Vsupply/2.

The CLC1007 is short circuit protected. However, this may

not guarantee that the maximum junction temperature

(+150°C) is not exceeded under all conditions. Figure 6

shows the maximum safe power dissipation in the package

vs. the ambient temperature for the packages available.

0.5

1.5

2.5

-40

-20

100

120

Ambient Temperature (°C)

MSOP-8

SOIC-8

TSSOP-14

TSOT-5

SOIC-14

Figure 6. Maximum Power Derating

Driving Capacitive Loads

Increased phase delay at the output due to capacitive loading

can cause ringing, peaking in the frequency response, and

possible unstable behavior. Use a series resistance, RS,

between the amplifier and the load to help improve stability

and settling performance. Refer to Figure 7.

Input

Output

Figure 7. Addition of RS for Driving Capacitive Loads

Table 1 provides the recommended RS for various capacitive

loads. The recommended RS values result in approximately

<1dB peaking in the frequency response.

CL (pF)

RS (Ω)

-3dB BW (MHz)

22pF

118

47pF

112

100pF

492pF

6.5

Table 1: Recommended RS vs. CL

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