8

Rev. C - 15 January, 2001

TS80C31X2

Table 3. CKCON Register

CKCON - Clock Control Register (8Fh)

Reset Value = XXXX XXX0b

Not bit addressable

For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com)

7

6

5

4

3

2

1

0

-

-

-

-

-

-

-

X2

Bit

Number

Bit

Mnemonic

Description

7

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0

X2

CPU and peripheral clock bit