© VITESSE SEMICONDUCTOR CORPORATION

Page 3

9/29/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC8115

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

G52272-0, Rev. 1.1

Figure 1: Control Diagram for Signal Detection and PLL Bypass Operation

Table 1: Signal Detection and PLL Bypass Operation Control

STS12

BYPASS

LOCKREFN

SD

LOS

DATAOUT

CLKOUT

1

0

1

1

0

DATIN

PLL Clock

1

0

1

0

1

LOW

PLL Clock

1

0

0

1

1

LOW

PLL Clock

1

0

0

0

1

LOW

PLL Clock

1

1

X

X

0

DATIN

REFCLK

0

0

1

1

0

DATIN

PLL Clock

0

0

1

0

1

LOW

PLL Clock

0

0

0

1

1

LOW

PLL Clock

0

0

0

0

1

LOW

PLL Clock

0

1

X

X

0

Not Allowed

Not Allowed

1

0

2

CLKOUT+/-±

DATAOUT+/-

BYPASS

DATAIN+/-

STS12

REFCLK

2

PLL Clock

(on-chip)

2

LOCKREFN

SD

LOS

(on-chip)