DS2156L datasheet(91/262 Pages) DALLAS

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DS2156

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SIGCR

Signaling Control Register

40h

Bit #

Name

GRSRE

—

RFE

RFF

RCCS

TCCS

FRSAO

Default

Bit 0/Force Receive Signaling All Ones (FRSAO). In T1 mode, this bit forces all signaling data at the RSIG and

RSER pin to all ones. This bit has no effect in E1 mode.

0 = normal signaling data at RSIG and RSER

1 = force signaling data at RSIG and RSER to all ones

Bit 1/Transmit Time Slot Control for CAS Signaling (TCCS). Controls the order that signaling is transmitted

from the transmit signaling registers. This bit should be set = 0 in T1 mode.

0 = signaling data is CAS format

1 = signaling data is CCS format

Bit 2/Receive Time Slot Control for CAS Signaling (RCCS). Controls the order that signaling is placed into the

receive signaling registers. This bit should be set = 0 in T1 mode.

0 = signaling data is CAS format

1 = signaling data is CCS format

Bit 3/Receive Force Freeze (RFF). Freezes receive-side signaling at RSIG (and RSER if receive signaling

reinsertion is enabled); overrides receive freeze enable (RFE). See Section 15.1.2.3 for details.

0 = do not force a freeze event

1 = force a freeze event

Bit 4/Receive Freeze Enable (RFE). See Section 15.1.2.3 for details.

0 = no freezing of receive signaling data occurs

1 = allow freezing of receive signaling data at RSIG (and RSER if receive signaling reinsertion is enabled)

Bits 5, 6/Unused, must be set to 0 for proper operation

Bit 7/Global Receive Signaling Reinsertion Enable (GRSRE). This bit allows the user to reinsert all signaling

channels without programming all channels through the per-channel function.

0 = do not reinsert all signaling

1 = reinsert all signaling

DS2156L 데이터시트(PDF) 91 Page - Dallas Semiconductor