2004 Sep 10

2

Philips Semiconductors

Product specification

Dual buffer gate

74LVC2G34

FEATURES

• Wide supply voltage range from 1.65 V to 5.5 V

• 5 V tolerant input/output for interfacing with 5 V logic

• High noise immunity

• Complies with JEDEC standard:

– JESD8-7 (1.65 V to 1.95 V)

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V).

• ESD protection:

– HBM EIA/JESD22-A114-B exceeds 2000 V

– MM EIA/JESD22-A115-A exceeds 200 V.

• CMOS low power consumption

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Multiple package options

• Specified from −40 °C to +85 °C and

−40 °C to +125 °C.

DESCRIPTION

The 74LVC2G34 is a high-performance, low-power,

low-voltage, Si-gate CMOS device and superior to most

advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices.

These feature allows the use of these devices as

translators in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down

preventing the damaging backflow current through the

device when it is powered down.

The 74LVC2G34 provides two buffers.

QUICK REFERENCE DATA

Notes

N = total load switching outputs;

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

propagation delay input nA to output nY

3.8

ns

2.4

ns

2.5

ns

2.2

ns

1.9

ns

input capacitance

2.5

pF

power dissipation capacitance

20

pF