전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

CS61535A 데이터시트(PDF) 24 Page - Cirrus Logic

부품명 CS61535A
상세설명  T1/E1 LINE INTERFACE
PDF  48 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS61535A 데이터시트(HTML) 24 Page - Cirrus Logic

Back Button CS61535A Datasheet HTML 20Page - Cirrus Logic CS61535A Datasheet HTML 21Page - Cirrus Logic CS61535A Datasheet HTML 22Page - Cirrus Logic CS61535A Datasheet HTML 23Page - Cirrus Logic CS61535A Datasheet HTML 24Page - Cirrus Logic CS61535A Datasheet HTML 25Page - Cirrus Logic CS61535A Datasheet HTML 26Page - Cirrus Logic CS61535A Datasheet HTML 27Page - Cirrus Logic CS61535A Datasheet HTML 28Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 48 page
background image
Power Supplies
RGND - Ground, Pin 22.
Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.
RV+ - Power Supply, Pin 21.
Power supply for all subcircuits except the transmit driver; typically +5 Volts.
TGND - Ground, Transmit Driver, Pin 14.
Power supply ground for the transmit driver; typically 0 Volts.
TV+ - Power Supply, Transmit Driver, Pin 15.
Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than
0.3 V.
Oscillator
XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.
A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or
2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying
XTALIN, Pin 9 to RV+ through a 1 k
Ω resistor, and floating XTALOUT, Pin 10.
Overdriving the oscillator with an external clock is not supported.
Control
ACLKI - Alternate External Clock Input, Pin 1.
The CS61535A does not require a clock signal to be input on ACLKI when a crystal is connected
between pins 9 and 10. If a clock is not provided on ACLKI, this input must be grounded. If
ACLKI is grounded, the oscillator in the jitter attenuator is used to calibrate the clock recovery
circuit and TAOS is not available.
CLKE - Clock Edge, Pin 28. (Host Mode)
Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and
SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS
and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of
SCLK.
CS - Chip Select, Pin 26. (Host Mode)
This pin must transition from high to low to read or write the serial port.
INT - Receive Alarm Interrupt, Pin 23. (Host Mode)
Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing
"Clear LOS" or "Clear DPM" to the register. INT is an open drain output and should be tied to
the power supply through a resistor.
CS61535A
24
DS40F1



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com