Supertex inc.

Supertex inc.

www.supertex.com

Doc.# DSFP-TP5322

C081613

TP5322

General Description

The Supertex TP5322 is a low threshold enhancement-

mode (normally-off) transistor utilizing an advanced vertical

DMOS structure and Supertex’s well-proven silicon-gate

manufacturing process. This combination produces a device

with the power handling capabilities of bipolar transistors

and with the high input impedance and positive temperature

coefficient inherent in MOS devices. Characteristic of all

MOS structures, this device is free from thermal runaway and

thermally-induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications where

high breakdown voltage, high input impedance, low input

capacitance, and fast switching speeds are desired.

Features

Applications

TO-243AA (SOT-89)

TO-243AA (SOT-89)

GATE

SOURCE

DRAIN

DRAIN

TP3CW

W = Code for week sealed

= “Green” Packaging

Pin Configuration

Product Marking

TO-236AB (SOT-23)

P3CW

W = Code for week sealed

= “Green” Packaging

DRAIN

SOURCE

GATE

TO-236AB (SOT-23)

Package may or may not include the following marks: Si or

Package may or may not include the following marks: Si or

P-Channel Enhancement-Mode

Vertical DMOS FET

Absolute Maximum Ratings

Parameter

Value

Drain-to-source voltage

BV

DSS

Drain-to-gate voltage

BV

DGS

Gate-to-source voltage

±20V

Operating and storage temperature

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

Ordering Information

Part Number

Package Option

Packing

TP5322K1-G

TO-236AB (SOT-23)

3000/Reel

TP5322N8-G

3-Lead TO-92

2000/Reel

Product Summary

BV

R

DS(ON)

(max)

I

D(ON)

(min)

V

GS(th)

(max)

-220V

12Ω

-700mA

-2.4V

-G denotes a lead (Pb)-free / RoHS compliant package.

Contact factory for Wafer / Die availablity.

Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.

Typical Thermal Resistance

Package

θ

ja

TO-236AB (SOT-23)

TO-243AA (SOT-89)