GL811USB datasheet(17/36 Pages) ETC

17 / 36 page

GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller

Page 16

3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.

3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is

released prior to negation and may be asserted for no more than 5 ns before release: no

wait generated.

3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be

asserted for no more than 5 ns before release: wait generated. The cycle completes after

IORDY is released. For cycles where a wait is generated and DIOR_ is asserted, the

device shall read data on IODD(0:7) for tRD before asserting IORDY.

4.DMACK_ shall remain negated during a register transfer.

Timing (ns)

Cycle time

2000

Address valid to DIOR_/ DIOW_ setup

1000

DIOR_/ DIOW_ pulse width 8-bit

300

t2i

DIOR_/ DIOW_ recovery time

900

DIOW_ data setup

DIOW_ data hold

DIOR_ data setup

DIOR_ data hold

t6Z

DIOR_ data tristate

DIOR_/ DIOW_ to address valid hold

900

tRD

Read Data Valid to IORDY active

(if IORDY initially low after tA)

IORDY Setup time

IORDY Pulse Width

IORDY assertion to release (max)

GL811USB 데이터시트(PDF) 17 Page - List of Unclassifed Manufacturers