PI2007 datasheet(17/19 Pages) VICOR

17 / 19 page

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Picor Corporation • picorpower.com

PI2007

Rev 1.3

Page 17 of 19

Layout Recommendation:

Use the following general guidelines when designing

printed circuit boards. An example of the typical land

pattern for a DFN PI2007 and SO-8/PowerPak

MOSFET is shown in Figure 21 and Figure 22:



It is best to connect the gate of the MOSFET to

the GATE pin of the controller with a short trace. A

gate resistor (RG) is added to slow down the gate

turn off if needed.



The VC bypass capacitor should be located as

close as possible to the VC and SGND pins.

Place the PI2007 and VC bypass capacitor on the

same layer of the board.

The VC pin and CVC

PCB trace should not contain any vias.



In an application where SGND is floating, a low

forward voltage drop Schottky diode has to be

added in parallel with CVC to protect the controller

during an input voltage short fault.



PGND pin of the controller carries high peak

current during gate pull down, Connect PGND pin

with a wide trace to the CVC terminal at SGND.

Make sure that SGND trace and PGND trace

connect only at CVC terminal.



Connections from the SP and SN pins to the

MOSFET source and drain pins respectively

should be as short as possible



Connect all MOSFET source pins together with a

wide trace to reduce trace parasitics and to

accommodate the high current input. Similarly,

connect all MOSFET Drain pins together with a

wide trace to accommodate the high current

output.

Figure 21: PI2007 controller and MOSFET layout

recommendation in a floating application.

Figure 22: PI2007 controller and MOSFET layout

recommendation in a non-floating application

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