LE25U40CMC

www.onsemi.com

15

12. Hold Function

Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure17

HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic

level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high,

HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited

and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state,

and SI and SCK are "don't care".

Figure 17 HOLD

13. Power-on

In order to protect against unintentional writing, CS must be within at VDD-0.3 to VDD+0.3 on power-on. After power-

on, the supply voltage has stabilized at VDD min. or higher, waits for tPU before inputting the command to start a

device operation. The device is in the standby state and not in the power-down state after power is turned on. To put the

device into the power-down state, it is necessary to enter a power-down command.

Figure 18 Power-on Timing

CS

HOLD

SCK

SO

Active

HOLD

Active

tHH

tHS

tHLZ

tHHZ

High Impedance

tHH

tHS

VDD(Max)

VDD(Min)

VDD

0V

tPU

CS = VDD level

Full Access Allowed