EP7312 datasheet(13/54 Pages) CIRRUS

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DS506PP1

©Copyright Cirrus Logic, Inc. 2003

EP7311

High-Performance, Low-Power System on Chip

SDRAM Interface

Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the

values for the timings ofeach ofthe SDRAM modes.

Parameter

Symbol

Min

Typ

Max

Unit

SDCLK rising edge to SDCS assert delay time

tCSa

SDCLK rising edge to SDCS deassert delay time

tCSd

− 32

SDCLK rising edge to SDRAS assert delay time

tRAa

SDCLK rising edge to SDRAS deassert delay time

tRAd

− 31

SDCLK rising edge to SDRAS invalid delay time

tRAnv

SDCLK rising edge to SDCAS assert delay time

tCAa

− 22

SDCLK rising edge to SDCAS deassert delay time

tCAd

− 50

SDCLK rising edge to ADDR transition time

tADv

− 31

SDCLK rising edge to ADDR invalid delay time

tADx

− 22

SDCLK rising edge to SDMWE assert delay time

tMWa

− 21

SDCLK rising edge to SDMWE deassert delay time

tMWd

− 40

DATA transition to SDCLK rising edge time

tDAs

SDCLK rising edge to DATA transition hold time

tDAh

SDCLK rising edge to DATA transition delay time

tDAd

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