 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
PC87427 데이터시트(PDF) 39 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87427 데이터시트(HTML) 39 Page - National Semiconductor (TI) |
|
|
39 / 46 page  2.0 Device Characteristics (Continued) Revision 1.0 39 www.national.com 2.5.8 FDC Timing FDC Write Data Timing tDRP tICP tWDW Values FDC Drive Control Timing Symbol Parameter Min Max Unit tHDH HDSEL Hold from WGATE Inactive1 1. Not tested. Guaranteed by design. 100 µs tHDS HDSEL Setup to WGATE Active1 100 µs tWDW Write Data Pulse Width1 See tDRP,tICP and tWDW values in table below Data Rate tDRP tICP tICP Nominal tWDW tWDW Minimum Unit 1 Mbps 1000 6xtCP 1 1. tCP is the clock period defined for CLKIN in Clock Timing on page 30. 125 2 x tICP 250 ns 500 Kbps 2000 6xtCP 1 125 2 x tICP 250 ns 300 Kbps 3333 10 x tCP 1 208 2 x tICP 375 ns 250 Kbps 4000 12 x tCP 1 250 2 x tICP 500 ns Symbol Parameter Min Max Unit tDST DIR Setup to STEP Active1 1. Not tested. Guaranteed by design. 6 µs tIW Index Pulse Width 100 ns tSTD DIR Hold from STEP Inactive tSTR ms tSTP STEP Active High Pulse Width1 8 µs tSTR STEP Rate Time1 0.5 ms tHDS tHDH tWDW HDSEL WGATE WDATA |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
