The components shown will add poles and zeros to the loop

gain as given by the following equations:

C10 adds a pole whose frequency is given by:

f

C12 adds a pole whose frequency is given by:

f

R11 adds a zero whose frequency is given by:

f

The output capacitor adds both a pole and a zero to the loop:

f

f

Where R

series resistance of the output capacitor(s).

The function of the compensation components will be ex-

plained in a qualitative discussion of a typical loop gain plot

for an LM2641 application, as illustrated in

Figure 5.

C10 and R11 form a pole and a zero. Changing the value of

C10 moves the frequency of both the pole and the zero.

Changing R11 moves the zero without significantly affecting

the pole.

The C10 pole is typically referred to as the dominant pole,

and its primary function is to roll off loop gain and reduce the

bandwidth.

The R11 zero is required to add some positive phase shift to

offset some of the negative phase shift from the two

low-frequency poles. Without this zero, these two poles

would cause −180˚ of phase shift at the unity-gain crossover,

which is clearly unstable. Best results are typically obtained

if R11 is selected such that the frequency of f

range of f

quency.

The output capacitor (along with the load resistance R

forms a pole shown as f

this pole varies with R

ally which means the unity-gain crossover frequency stays

essentially constant regardless of R

C12 can be used to create an additional pole most often

used for bypassing high-frequency switching noise on the

COMP pin. In many applications, this capacitor is unneces-

sary.

If C12 is used, best results are obtained if the frequency of

the pole is set in the range F

bypassing for the high-frequency noise caused by switching

transitions, but add only a small amount of negative phase

shift at the unity-gain crossover frequency.

The ESR of C

the zero f

10kHz and 50kHz. This zero is very important, as it cancels

phase shift caused by the high-frequency pole f

important to select C

tance and ESR to place this zero near f

f

As an example, we will present an analysis of the loop gain

plot for a 3.3V design. Values used for calculations are:

V

V

C

ESR = 60 m

Ω(each) = 30mΩ total

F

f

R13 = 20m

Ω

L2 = 6.8 µH

R

DC gain = 55dB

The values of compensation components will be: C10 =

2200 pF, R11 = 8.2k, and C12 will not be used. Using this

data, the poles and zeros are calculated:

f

f

f

f

f

Using these values, the calculated gain plot is shown in

Fig-

ure 6.

DS100949-5

FIGURE 4. Typical Compensation Network

DS100949-6

FIGURE 5. Typical Loop Gain Plot

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