PCB LAYOUT CONSIDERATIONS

Layout is critical to reduce noise and ensure specified perfor-

mance. The important guidelines are listed as follows:

1.

Minimize the parasitic inductance in the loop of input ca-

pacitors and the internal MOSFETs by connecting the in-

put capacitors to V

traces. The high frequency ceramic bypass capacitor, in

particular, should be placed as close to and no more

than 5mm from the V

the rapidly switching current, together with wiring induc-

tance can generate large voltage spikes that may result

in noise problems.

2.

Minimize the trace from the center of the output resistor

divider to the FB pin and keep it away from noise

sources to avoid noise pick up. For applications that re-

quire tight regulation at the output, a dedicated sense

trace (separated from the power trace) is recommended

to connect the top of the resistor divider to the output.

3.

If the Schottky diode D is used, minimize the traces con-

necting D to SW and PGND pins. Use short and wide

traces.

4.

If the low-side MOSFET is used, minimize the trace con-

necting the LDR pin to the gate of the MOSFET, and the

traces to SW and PGND pins. Use short and wide traces

for the power traces going from the MOSFET to SW and

PGND pins.

DS101284-24

FIGURE 5. Obtaining output voltages of less than 1.25V

DS101284-25

Schematic for the Typical Board Layout

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