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MPC9350 데이터시트(PDF) 2 Page - Motorola, Inc |
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MPC9350 데이터시트(HTML) 2 Page - Motorola, Inc |
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2 / 12 page ![]() MPC9350 MOTOROLA TIMING SOLUTIONS 2 Figure 1. MPC9350 Logic Diagram PLL (pulldown) FBSEL FSELA QA REF_SEL 0 1 Ref FB 200 - 400 MHz ÷2 ÷4 ÷8 D Q QB 0 1 0 1 0 1 FSELB FSELC (pulldown) (pulldown) (pullup) (pulldown) PLL_EN FSELD D Q QC1 0 1 D Q QC0 QD2 0 1 D Q QD1 QD0 QD4 QD3 OE (pulldown) (pulldown) (pulldown) (pulldown) XTAL1 XTAL2 TCLK 0 1 ÷16 ÷32 GND QB VCCO QA GND TCLK PLL_EN QD2 VCCO QD3 GND QD4 VCCO XTAL2 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1234 5678 24 23 22 21 20 19 18 17 16 MPC9350 OE Figure 2. Pinout: 32–Lead Package Pinout (Top View) REF_SEL Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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