16F630 datasheet(49/132 Pages) MICROCHIP

49 / 132 page

 2003 Microchip Technology Inc.

DS40039C-page 47

PIC16F630/676

7.2

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (C

HOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 7-3. The source

impedance (R

S) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor C

HOLD. The sampling switch (RSS)

impedance varies over the device voltage (V

DD), see

Figure 7-3. The maximum recommended imped-

ance for analog sources is 10 k

Ω. As the impedance

is decreased, the acquisition time may be decreased.

After the analog input channel is selected (changed),

this acquisition must be done before the conversion

can be started.

To calculate the minimum acquisition time, Equation 7-1

may be used. This equation assumes that 1/2 LSb error

is used (1024 steps for the A/D). The 1/2 LSb error is the

maximum error allowed for the A/D to meet its specified

resolution.

To calculate the minimum acquisition time, T

ACQ, see

the

PICmicro™

Mid-Range

Reference

Manual

(DS33023).

EQUATION 7-1:

ACQUISITION TIME

FIGURE 7-3:

ANALOG INPUT MODEL

ACQ

Amplifier Settling Time +

Hold Capacitor Charging Time +

Temperature Coefficient

AMP + TC + TCOFF

µs + TC + [(Temperature -25°C)(0.05µs/°C)]

HOLD (RIC + RSS + RS) In(1/2047)

- 120pF (1k

Ω + 7kΩ + 10kΩ) In(0.0004885)

16.47

µs

µs + 16.47µs + [(50°C -25°C)(0.05µs/°C)

19.72

µs

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (C

HOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k

Ω. This is required to meet the pin

leakage specification.

CPIN

ANx

5 pF

VDD

VT = 0.6V

T = 0.6V

I LEAKAGE

RIC

≤ 1K

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

Sampling Switch

567 8 9 10 11

Ω)

VDD

= 120 pF

± 500 nA

Legend CPIN

I LEAKAGE

RIC

HOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

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