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LIS3MDL

Digital interfaces

5.1.1

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first seven bits

and the eighth bit tells whether the master is receiving data from the slave or transmitting

data to the slave. When an address is sent, each device in the system compares the first

seven bits after a start condition with its address. If they match, the device considers itself

addressed by the master.

The Slave ADdress (SAD) associated to the LIS3MDL is 00111x0b, whereas the x bit is

modified by the SDO/SA1 pin in order to modify the device address. If the SDO/SA1 pin is

connected to the voltage supply, the address is 0011110b, otherwise, if the SDO/SA1 pin is

connected to ground, the address is 0011100b.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver

which has been addressed is obliged to generate an acknowledge after each byte of data

received.

protocol must be adhered to. After the START condition (ST) a slave address is sent, once a

slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the

7 LSb represent the actual register address while the MSb enables address auto-increment.

If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to

allow multiple data read/write.

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)

the master will transmit to the slave with direction unchanged. Table 11 explains how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Table 11. SAD+read/write patterns

Command

SAD[6:2]

SAD[1] = SDO/SA1

SAD[0]

R/W

SAD+R/W

Read

00111

0

0

1

00111001 (39h)

Write

00111

0

0

0

00111000 (38h)

Read

00111

1

0

1

00111101 (3Dh)

Write

00111

1

0

0

00111100 (3Ch)

Table 12. Transfer when master is writing one byte to slave

Master

ST

SAD + W

SUB

DATA

SP

Slave

SAK

SAK

SAK