TMS320DM642 datasheet(72/178 Pages) TI

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DM642 Peripheral Information and Electrical Specifications

5.1

Parameter Information

5.1.1

Parameter Information Device-Specific Information

Transmission Line

4.0 pF

1.85 pF

Z0 = 50

Ω

(see note)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output

Under

Test

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must

be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The

transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data

sheet timings.

Ω

3.5 nH

Device Pin

(see note)

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Vref = 1.5 V

Vref = VIL MAX (or VOL MAX or

Vref = VIH MIN (or VOH MIN or

VIHP MIN or VOHP MIN)

VILP MAX or VOLP MAX)

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

Figure 5-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

5.1.1.1

Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.

Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,

VOLMAX and VOH MIN for output clocks, VILP MAX and VIHP MIN for PCI input clocks, and VOLP MAX and

VOHP MIN for PCI output clocks.

Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels

DM642 Peripheral Information and Electrical Specifications

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