PM8313 datasheet(67/192 Pages) PMC

67 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Bit

Type

Function

Default

Bit7

R/W

REXHDLC

Bit6

R/W

TEXHDLC

Bit5

Unused

Bit4

Unused

Bit3

R/W

REOMPOL

Bit2

R/W

TUDRPOL

Bit1

R/W

RINTPOL

Bit0

R/W

TINTPOL

The Master HDLC Configuration Register is provided at D3MX read/write

address 03H.

REXHDLC:

The state of the receive external HDLC (REXHDLC) bit determines whether

the C-bit parity path maintenance data link is terminated by the internal HDLC

receiver or by an external HDLC receiver. When the REXHDLC bit is a logic

0, the internal HDLC receiver is selected; the RDLCLK/RDLINT pin is

configured to output the interrupt signal (RDLINT) from the internal HDLC

receiver and the RDLSIG/RDLEOM pin is configured to output the end-of-

message signal (RDLEOM) from the internal HDLC receiver. When the

REXHDLC bit is a logic 1, the use of an external HDLC receiver is selected;

the RDLSIG/RDLEOM pin is configured to output the data link data stream

(RDLSIG) and the RDLCLK/RDLINT pin is configured to output the data link

clock signal (RDLCLK). The REXHDLC bit is cleared to logic 0 upon reset.

TEXHDLC:

The state of the transmit external HDLC (TEXHDLC) bit determines whether

the C-bit parity path maintenance data link is sourced by the internal HDLC

transmitter or by an external HDLC transmitter. When the TEXHDLC bit is a

logic 0, the internal HDLC transmitter is selected; the TDLCLK/TDLINT pin is

configured as an output to present the interrupt signal (TDLINT) from the

internal HDLC transmitter and the TDLSIG/TDLUDR pin is configured to

output the underrun signal (TDLUDR) from the internal HDLC transmitter.

When the TEXHDLC bit is a logic 1, the use of an external HDLC transmitter

is selected; the TDLSIG/TDLUDR pin is configured to input the data link data

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