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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM8AL3L48 데이터시트(PDF) 88 Page - STMicroelectronics |
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STM8AL3L48 데이터시트(HTML) 88 Page - STMicroelectronics |
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88 / 124 page  Electrical parameters STM8AL313x/4x/6x STM8AL3L4x/6x 88/124 DocID18474 Rev 7 Figure 30. Typical NRST pull-up current Ipu vs VDD The reset network shown in Figure 31 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 45. Otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, attention must be paid to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. The minimum recommended capacity is 10 nF. Figure 31. Recommended NRST pin configuration |
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