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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD9755AST 데이터시트(PDF) 3 Page - Analog Devices |
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AD9755AST 데이터시트(HTML) 3 Page - Analog Devices |
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3 / 26 page  REV. 0 –3– AD9753 (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, Differential Transformer Coupled Output, 50 Doubly Terminated, unless otherwise noted.) DYNAMIC SPECIFICATIONS Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (fDAC) 300 MSPS Output Settling Time (tST) (to 0.1%) 1 11 ns Output Propagation Delay (tPD) 1 1ns Glitch Impulse 1 5 pV-s Output Rise Time (10% to 90%) 1 2.5 ns Output Fall Time (10% to 90%) 1 2.5 ns Output Noise (IOUTFS = 20 mA) 50 pA/ √Hz Output Noise (IOUTFS = 2 mA) 30 pA/ √Hz AC LINEARITY Spurious-Free Dynamic Range to Nyquist fDAC = 100 MSPS; fOUT = 1.00 MHz 0 dBFS Output 72 82 dBc –6 dBFS Output 76 dBc –12 dBFS Output 76 dBc fDATA = 65 MSPS; fOUT = 1.1 MHz 2 77 dBc fDATA = 65 MSPS; fOUT = 5.1 MHz 2 77 dBc fDATA = 65 MSPS; fOUT = 10.1 MHz 2 76 dBc fDATA = 65 MSPS; fOUT = 20.1 MHz 2 72 dBc fDATA = 65 MSPS; fOUT = 30.1 MHz 2 68 dBc fDAC = 200 MSPS; fOUT = 1.1 MHz 78 dBc fDAC = 200 MSPS; fOUT = 11.1 MHz 75 dBc fDAC = 200 MSPS; fOUT = 31.1 MHz 70 dBc fDAC = 200 MSPS; fOUT = 51.1 MHz 70 dBc fDAC = 200 MSPS; fOUT = 71.1 MHz 67 dBc fDAC = 300 MSPS; fOUT = 1.1 MHz 78 dBc fDAC = 300 MSPS; fOUT = 26.1 MHz 69 dBc fDAC = 300 MSPS; fOUT = 51.1 MHz 65 dBc fDAC = 300 MSPS; fOUT = 101.1 MHz 59 dBc fDAC = 300 MSPS; fOUT = 141.1 MHz 58 dBc Spurious-Free Dynamic Range within a Window fDAC = 100 MSPS; fOUT = 1 MHz; 2 MHz Span 0 dBFS Output 82.5 92 dBc fDAC = 65 MSPS; fOUT = 5.02 MHz; 2 MHz Span 85 dBc fDAC = 150 MSPS; fOUT = 5.04 MHz; 4 MHz Span 85 dBc Total Harmonic Distortion fDAC = 100 MSPS; fOUT = 1.00 MHz 0 dBFS –82 –71 dBc fDAC = 65 MHz; fOUT = 2.00 MHz –76 dBc fDAC = 160 MHz; fOUT = 2.00 MHz –76 dBc Multitone Power Ratio (Eight Tones at 110 kHz Spacing) fDAC = 65 MSPS; fOUT = 2.00 MHz to 2.77 MHz 0 dBFS Output 73 dBc –6 dBFS Output 71 dBc –12 dBFS Output 69 dBc NOTES 1Measured single-ended into 50 Ω load. 2Single-Port Mode (PLL disabled, DIV0 = 1, DIV1 = 0, data on Port 1). Specifications subject to change without notice. |
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