STM8AL3188TCX datasheet(17/131 Pages) STMICROELECTRONICS

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DocID027179 Rev 6

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STM8AL318x STM8AL3L8x

Functional overview

3.3

Reset and supply management

3.3.1

Power supply scheme

The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power

supply pins must be connected as follows:

•

VSS1, VDD1, VSS2, VDD2, VSS3, VDD3, VSS4, VDD4= 1.65 to 3.6 V: external power supply

for I/Os and for the internal regulator. Provided externally through VDD pins, the

corresponding ground pin is VSS. VSS1/VSS2/VSS3/VSS4 and VDD1/VDD2/VDD3/VDD4

must not be left unconnected.

•

VSSA, VDDA = 1.65 to 3.6 V: external power supplies for analog peripherals (minimum

voltage to be applied to VDDA is 1.8 V when the ADC1 is used). VDDA and VSSA must

be connected to VDD and VSS, respectively.

•

VREF+, VREF- (for ADC1): external reference voltage for ADC1. Must be provided

externally through VREF+ and VREF- pin.

•

VREF+ (for DAC1/2): external voltage reference for DAC1 and DAC2 must be provided

externally through VREF+.

3.3.2

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active,

and ensures proper operation starting from 1.8 V. As soon as the 1.8 V BOR threshold is

reached, the option byte loading process starts, either to confirm or modify the default

thresholds, or to disable BOR permanently. In this latter case, the VDD min value at power

down is 1.65 V.

Five BOR thresholds are available through option byte, starting from 1.8 V to 3 V. To reduce

the power consumption in Halt mode, it is possible to automatically switch off the internal

reference voltage (and consequently the BOR) in Halt mode. The device remains in reset

state when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An

interrupt is generated when VDD/VDDA drops below the VPVD threshold and/or when

VDD/VDDA is higher than the VPVD threshold. The interrupt service routine generates then a

warning message and/or put the MCU into a safe state. The PVD is enabled by software.

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