MD1730 datasheet(17/34 Pages) MICROCHIP

17 / 34 page

 2016 Microchip Technology Inc.

DS20005586B-page 17

MD1730

D12 = 1, W/R bit set equal to high for write

operation.

ADD<11:8> = 0011b, address for channel-3’s

phase delay register.

D<7:0> = 01010101b, data to be written into

channel-3’s phase delay register.

The SDI data is shifted in at the rising edge of

SCK.

Once the complete data has been shifted in, the

CSN should be taken high to finish the writing

operation. The SDI data is latched into

channel-3’s phase delay register on the rising

edge of the CSN signal. CSN has to be kept high

for a minimum of 2-SCK cycles for the data to be

written into the appropriate register.

In the case of eight chips daisy chained together as

shown in Figure 4-3, there should be 13 x 8 = 104

cycles of SCK before the CSN is taken high.

The MD1730 can also be used in the Broadcasting

mode to write several daisy chained chips with the

same data. The Broadcasting mode can be used to

reduce the time required to write the SPI if several

MD1730 chips need the same data. The following is a

1-byte writing example for the register at the address

location ADD = 0011b with data D<7:0> =01010101b

while the MD1730 is set to broadcasting mode.

The write operation starts with setting CSN to

low with TXRW = 0 and SPIB = 1.

The SCK clock is used to shift in the following

SDI data to the first MD1730 chip:

D12 = 1, W/R bit set equal to high for write

operation.

ADD<11:8> = 0011b,

address

for

the

channel-3’s phase delay register.

D<7:0> = 01010101, data to be written into the

channel-3’s phase delay register.

The SDI data is shifted in at the rising edge of

SCK.

In Broadcasting mode, the same set of data

shifted into the first chip’s SDI is sent to all the

MD1730 chips along the daisy chain. As shown

is Figure 4-3 when SPIB = 1 an internal switch

connects the SDI and SDO directly.

Once the complete data has been shifted in, the

CSN should be taken high to finish the writing

operation. The SDI data is latched into each

chip’s channel-3 phase delay register on the

rising edge of the CSN signal. CSN has to be

kept high for a minimum of 2-SCK cycles for the

data to be written into the appropriate register.

4.4.2

SPI READ OPERATION EXAMPLES

The following is a 2-byte reading example from the

The read operation starts with setting CSN to

low.

The SCK clock is used to shift in the following

SDI data:

D12 = 0, W/R bit set equal to high for read

operation.

ADD<11:8> = 0011b, address for channel-3’s

phase delay register.

D<7:0> = X, for a Read operation the data field

is don’t’ care.

The SDI data is shifted in at the rising edge of

SCK.

Once the complete data has been shifted into

the SPI the CSN is taken high. While CSN is

high the MD1730 fetches the data located at

ADD<11:9> = 0011b and places it in its internal

shift register.

Once the complete data has been shifted in, the

CSN should be taken high to finish the reading

operation. While CSN is high the MD1730

fetches the data located at ADD<11:9> = 0011b

and places it in its internal shift register. CSN

has to be kept high for a minimum of 2-SCK

cycles for the data to be fetched and placed into

the internal shift register.

The CSN is taken low and during the next 13

SCK clock cycles, the fetched data in the

internal shift register is clocked out on the rising

edge of SCK from the SDO of the MD1730.

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