 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
TP5510N 데이터시트(PDF) 2 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
TP5510N 데이터시트(HTML) 2 Page - National Semiconductor (TI) |
|
|
2 / 12 page  Block Diagram TLH11186 – 2 FIGURE 1 Pin Description Symbol Function VBB Negative power supply pin VBB eb5V g 5% GNDA Analog ground All signals are referenced to this pin VFDO Analog output of the receive power ampli- fier VCC Positive power supply pin VCC ea5V g 5% Symbol Function FSD Decode frame sync pulse which enables BCLKR to shift data into DD FSD is an 8 kHz pulse train See Figures 2 and 3 for timing details DD Decode data input Data is shifted into DD following the FSD leading edge BCLKD CLKSEL The bit clock which shifts data into DD af- ter the FSD leading edge May vary from 64 kHz to 2048 MHz Alternatively may be a logic input which selects either 1536 MHz1544 MHz or 2048 MHz for master clock in synchronous mode and BCLKD is used for both encode and de- code directions (see Table 1) http www nationalcom 2 |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
