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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STGAP1ASTR 데이터시트(PDF) 53 Page - STMicroelectronics |
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STGAP1ASTR 데이터시트(HTML) 53 Page - STMicroelectronics |
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53 / 70 page  DocID029344 Rev 2 53/70 STGAP1AS Programming manual 70 9.2.1 CFG1 register (low voltage side) T The CFG1 register has the structure of Table 24. The CRC_SPI bit enables the CRC check on the SPI communication protocol. The UVLOD_EN bit enables the UVLO protection on VDD supply voltage. Table 23. Registers access Name Address Mask code CFG1 0x0C 0xFF CFG2 0x1D 0xFF CFG3 0x1E 0xFF CFG4 0x1F 0x3F CFG5 0x19 0x0F STATUS1 0x02 0xFF STATUS2 0x01 0x06 STATUS3 0x0A 0x1F TEST1 0x11 0x1F DIAG1CFG 0x05 0xFF DIAG2CFG 0x06 0xFF Table 24. CFG1 register - Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - CRC_SPI UVLOD_EN SD_FLAG DIAG_EN DTset INfilter Default/reset 0 0 1 0 00 00 Table 25. CRC enable CRC_SPI SPI communication protocol CRC enable 0 Disabled 1 Enabled Table 26. VDD supply voltage UVLO enable UVLOD_EN Supply voltage UVLOD enable 0 Disabled 1 Enabled |
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