TH71221 datasheet(25/44 Pages) MELEXIS

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TH71221

27 to 930MHz

FSK/FM/ASK Transceiver

39010 071221

Page 25 of 44

Data Sheet

Rev. 009

Nov/15

5.1.5 D – word

Name

Bits

Description

[16:0]

Feedback divider ratio in TX operation mode

64d .. 131071d

ERTM

[18:17]

Set the unlock condition of the PLL

2 clocks

4 clocks

8 clocks

16 clocks

#default

Set the maximum allowed number of reference clocks

(1/fRO) during the phase detector output signals (UP &

DOWN) can be in-consecutive.

LDTM

[20:19]

Set the lock condition of the PLL

4 clocks

16 clocks

64 clocks

256 clocks

#default

Set the minimum number of consecutive edges of phase

detector output cycles, without appearance of any unlock

condition.

MODCTRL

[21]

Set mode of modulation control:

external modulation control

#default

Modulation will be set via pin ASK/FSK.

internal modulation control

Modulation will be set via bit MODSEL (bit 19 in A-word). Nevertheless pin ASK/FSK must be

connected to either VCC or VEE.

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