REV. 0

AD9751

–5–

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Description

1

RESET

Internal Clock Divider Reset

2

CLK+

Differential Clock Input

3

CLK–

Differential Clock Input

4, 22

DCOM

Digital Common

5, 21

DVDD

Digital Supply Voltage

6

PLLLOCK

PLL Lock Indicator Output

7–16

P1B9–P1B0

Data Bits P1B9 to P1B0, Port 1

17–20, 33–36

RESERVED

23–32

P2B9–P2B0

Data Bits P2B9 to P2B0, Port 2

37, 38

DIV0, DIV1

Control inputs for PLL and input port selector mode, see Tables I and II for details.

39

REFIO

Reference Input/Output

40

FSADJ

Full-Scale Current Output Adjust

41

AVDD

Analog Supply Voltage

42

Differential DAC Current Output

43

Differential DAC Current Output

44

ACOM

Analog Common

45

CLKCOM

Clock and Phase-Locked Loop Common

46

LPF

PLL Loop Filter

47

PLLVDD

Phase-Locked Loop Supply Voltage

48

CLKVDD

Clock Supply Voltage

PIN CONFIGURATION

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

36

35

34

33

32

31

30

29

28

27

26

25

AD9751

RESERVED

RESERVED

RESERVED

RESERVED

P2B0–LSB

P2B1

P2B2

P2B3

P2B4

P2B5

P2B6

P2B7

RESET

CLK+

CLK–

DCOM

DVDD

PLLLOCK

MSB–P1B9

P1B8

P1B7

P1B6

P1B5

P1B4

RESERVED = NO

USER CONNECTIONS