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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ARM920T 데이터시트(PDF) 2 Page - List of Unclassifed Manufacturers |
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ARM920T 데이터시트(HTML) 2 Page - List of Unclassifed Manufacturers |
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2 / 12 page  ARM920T Page 2 © Copyright ARM Limited 2000. All rights reserved. DVI 0024A ARM Confidential - Draft ARM920T Macrocell The ARM920T macrocell is based on the ARM9TDMI Harvard architecture processor core, with an efficient five stage pipeline. The architecture of the processor core or integer unit is described in more detail page 9. To reduce the effect of main memory bandwidth and latency on performance, the ARM920T includes: • instruction cache • data cache •MMU •TLBs • write buffer • physical address TAG RAM Caches Two 16KB caches are implemented, one for instructions, the other for data, both with an 8-word line size. A 32-bit data bus connects each cache to the ARM9TDMI core allowing a 32-bit instruction to be fetched and fed into the instruction Decode stage of the pipeline at the same time as a 32-bit data access for the Memory stage of the pipeline. Cache lock-down Cache lock-down is provided to allow critical code sequences to be locked into the cache to ensure predictability for real-time code. The cache replacement algorithm can be selected by the operating system as either pseudo random or round-robin. Both caches are 64-way set- associative. Lock-down operates on a per-set basis Write buffer The ARM920T also incorporates a 16-entry write buffer, to avoid stalling the processor when writes to external memory are performed. PATAG RAM The ARM920T implements PATAG RAM to perform write-backs from the data cache. The physical address of all the lines held in the data cache is stored by the PATAG memory, removing the need for address translation when evicting a line from the cache. MMUs The standard ARM920T implements an enhanced ARMv4 MMU to provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI. The MMU features are: • standard ARMv4 MMU mapping sizes, domains, and access protection scheme • mapping sizes are 1MB sections, 64KB large pages, 4KB small pages and new 1KB tiny pages • access permissions for sections • access permissions for large pages and small pages can be specified separately for each quarter of the page (these quarters are called subpages) • 16 domains implemented in hardware • 64-entry instruction TLB and 64- entry data TLB • hardware page table walks • round-robin replacement algorithm (also called cyclic). ARM920T function block diagram ARM9TDMI Processor core (Integral EmbeddedICE) Write buffer ID[31:0] IMVA[31:0] WBPA[31:0] DPA[31:0] IPA[31:0] ASB Write back PATAG RAM CP15 R13 IVA[31:0] DVA[31:0] JTAG External coprocessor interface DD[31:0] Instruction cache Instruction MMU Data MMU Data cache R13 DINDEX[5:0] Trace interface port AMBA bus interface DMVA[31:0] |
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