AT89LS52 datasheet(21/39 Pages) ATMEL

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AT89LS52

2601A–12/01

Program

Memory

Lock Bits

The AT89LS52 has three lock bits that can be left unprogrammed (U) or can be programmed

(P) to obtain the additional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during

reset. If the device is powered up without a reset, the latch initializes to a random value and

holds that value until reset is activated. The latched value of EA must agree with the current

logic level at that pin in order for the device to function properly.

Programming

the Flash –

Parallel Mode

The AT89LS52 is shipped with the on-chip Flash memory array ready to be programmed. The

programming interface needs a high-voltage (12-volt) program enable signal and is compati-

ble with conventional third-party Flash or EPROM programmers.

The AT89LS52 code memory array is programmed byte-by-byte.

Programming Algorithm: Before programming the AT89LS52, the address, data, and control

signals should be set up according to the Flash programming mode table and Figures 13 and

14. To program the AT89LS52, take the following steps:

Input the desired memory location on the address lines.

Input the appropriate data byte on the data lines.

Activate the correct combination of control signals.

Raise EA/V

PP to 12V.

Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-

write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1

through 5, changing the address and data for the entire array or until the end of the

object file is reached.

Data Polling: The AT89LS52 features Data Polling to indicate the end of a byte write cycle.

During a write cycle, an attempted read of the last byte written will result in the complement of

the written data on P0.7. Once the write cycle has been completed, true data is valid on all out-

puts, and the next cycle may begin. Data Polling may begin any time after a write cycle has

been initiated.

Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY out-

put signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0

is pulled high again when programming is done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code

data can be read back via the address and data lines for verification. The status of the individ-

ual lock bits can be verified directly by reading them back.

Table 9. Lock Bit Protection Modes

Program Lock Bits

LB1

LB2

LB3

Protection Type

No program lock features

MOVC instructions executed from external program memory are

disabled from fetching code bytes from internal memory, EA is

sampled and latched on reset, and further programming of the

Flash memory is disabled

Same as mode 2, but verify is also disabled

Same as mode 3, but external execution is also disabled

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