Input

Signal

IN

13

TPA3128D2

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SLOS941A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: TPA3128D2

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Table 2. Recommended Input AC-Coupling Capacitors

GAIN

INPUT IMPEDANCE

INPUT CAPACITANCE

HIGH-PASS FILTER

20 dB

60 kΩ

1.5 µF

1.8 Hz

26 dB

30 kΩ

3.3 µF

1.6 Hz

32 dB

15 kΩ

5.6 µF

2.3 Hz

36 dB

9 kΩ

10 µF

1.8 Hz

Figure 27. Input Impedance

The input capacitors used should be a type with low leakage, such as quality electrolytic, tantalum, or ceramic

capacitors. If a polarized type is used the positive connection should face the input pins which are biased to 3

Vdc.

7.3.3 Startup and Shutdown Operation

The TPA3128D2 employs a shutdown mode of operation designed to reduce supply current (Icc) to the absolute

minimum level during periods of nonuse for power conservation. The SDZ input terminal should be held high

(see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low will

put the outputs to mute and the amplifier to enter a low-current state. Do not leave SDZ unconnected, because

amplifier operation would be unpredictable.

For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power

supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is

selected and cannot be changed until the next power-up.

7.3.4 PLIMIT Operation

The TPA3128D2 has a built-in voltage limiter that can be used to limit the output voltage level below the supply

rail, the amplifier operates as if it was powered by a lower supply voltage, and thereby limits the output power.

Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also

be used if tighter tolerance is required. Add a 1-µF capacitor from pin PLIMIT to ground to ensure stability.

Figure 28. Power Limit Example