MCP652 datasheet(24/62 Pages) MICROCHIP

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MCP651/1S/2/3/4/5/9

DS20002146D-page 24

 2009-2014 Microchip Technology Inc.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the Common

mode voltage (VCM) is below ground (VSS); see

Figure 2-15. Applications that are high-impedance may

need to limit the usable voltage range.

4.2.3

NORMAL OPERATION

The input stage of the MCP651/1S/2/3/4/5/9 op amps

uses a differential PMOS input stage. It operates at low

Common mode input voltage (VCM), with VCM up to

VDD – 1.3V and down to VSS – 0.3V. The input offset

voltage (VOS) is measured at VCM =VSS –0.3V and

VDD – 1.3V to ensure proper operation. See Figure 2-6

and Figure 2-7 for temperature effects.

When operating at very low non-inverting gains, the

output voltage is limited at the top by the VCM range

(< VDD –1.3V); see Figure 4-5.

FIGURE 4-5:

Unity-Gain Voltage

Limitations for Linear Operation.

4.3

Rail-to-Rail Output

4.3.0.1

Maximum Output Voltage

The Maximum Output Voltage (see Figure 2-16 and

Figure 2-17) describes the output range for a given

load. For instance, the output voltage swings to within

15 mV of the negative rail with a 1 k

 load tied to

VDD/2.

4.3.0.2

Output Current

Figure 4-6 shows the possible combinations of output

voltage (VOUT) and output current (IOUT). IOUT is

positive when it flows out of the op amp into the

external circuit.

FIGURE 4-6:

Output Current.

VIN

MCP65X

VDD

VOUT





OUT

1.3V

–



-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

IOUT (mA)

RL = 10Ω

RL = 100Ω

RL = 1 kΩ

VOH Limited

VOL Limited

(VDD = 5.5V)

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