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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MCP37231 데이터시트(PDF) 65 Page - Microchip Technology |
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MCP37231 데이터시트(HTML) 65 Page - Microchip Technology |
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65 / 144 page  2014-2016 Microchip Technology Inc. DS20005322D-page 65 MCP37231/21-200 AND MCP37D31/21-200 TABLE 4-17: OUTPUT TYPE VS. CONTROL PARAMETERS FOR DUAL-CHANNEL DDC EXAMPLE Output Type Control Parameter Register Descriptions Complex: I and Q EN_DSPP_2 = 1 0X79 Enable all digital post-processing functions for dual-channel operations EN_DDC1 = 1 0X80 Enable DDC1 block EN_NCO = 1 0X80 Enable 32-bit NCO HBFILTER_A = 1 0X80 Enable Half-Band Filter A, includes 2x decimation HBFILTER_B = 1 0X80 Enable Half-Band Filter B, includes 2x decimation EN_DDC_FS/8 = 0 0X80 NCO(fS/8/DER) is disabled EN_DDC2 = 0 0X81 DDC2 is disabled FIR_A<8:1> = 0x00 0X7B FIR A decimation filter is disabled FIR_B<7:0> = 0x00 0X7C FIR B decimation filter is disabled OUT_CLKRATE<3:0> 0X02 Output clock rate is not affected (no need to change) Real: RealA for Channel A and RealB for Channel B after NCO(fS/8/DER) Without Using Decimation Filter EN_DSPP_2 = 1 0X79 Enable all digital post-processing functions for dual-channel operations EN_DDC1 = 1 0X80 Enable DDC1 block EN_NCO = 1 0X80 Enable 32-bit NCO HBFILTER_A = 1 0X80 Enable Half-Band Filter A, includes 2x decimation HBFILTER_B = 1 0X80 Enable Half-Band Filter B, includes 2x decimation EN_DDC_FS/8 = 1 0X80 NCO(fS/8/DER) is enabled. This translates the input signal from DC to fS/8(1) EN_DDC2 = 1 0X81 DDC2 is enabled FIR_A<8:1> = 0x00 0X7B Decimation filter FIR A is disabled FIR_B<7:0> = 0x00 0X7C Decimation filter FIR B is disabled OUT_CLKRATE<3:0> = 0001 0X02 Adjust the output clock rate to divided by 2(2) Decimated Real: RealA_DEC for Channel A and RealB_DEC for Channel B after NCO(fS/8/DER) and Decimation Filter EN_DSPP_2 = 1 0X79 Enable all digital signal post-processing functions for dual- channel operation EN_DDC1 = 1 0X80 Enable DDC1 block EN_NCO = 1 0X80 Enable 32-bit NCO HBFILTER_A = 1 0X80 Enable Half-Band Filter A, includes 2x decimation HBFILTER_B = 1 0X80 Enable Half-Band Filter B, includes 2x decimation EN_DDC_FS/8 = 1 0X80 NCO(fS/8/DER) is enabled. This translates the input signal from DC to fS/8/DER(1) EN_DDC2 = 1 0X81 DDC2 is enabled FIR_A<8:1> 0X7B Program FIR A filter for extra decimation(3) FIR_B<7:0> 0X7C Program FIR B filter for extra decimation(3) OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the total decimation rate including the 2x decimation by the Half-Band Filter A Note 1: DER is the decimation rate setting of the FIR A and FIR B filters. 2: Divided by 2 is due to the 2x decimation included in the Half-Band Filter A. 3: When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER). |
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