6

Integrated

Circuit

Systems, Inc.

ICS950202

0461L—05/28/03

Byte 1: Output Control Register

(1 = enable, 0 = disable)

Byte 3: Output Control Register

(1 = enable, 0 = disable)

Byte 2: Output Control Register

(1 = enable, 0 = disable)

Byte 4: Output Control Register

(1 = enable, 0 = disable)

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B9

3

,

0

41

2

C

/

T

U

P

C

6

t

i

B3

4

,

4

41

1

C

/

T

U

P

C

5

t

i

B6

4

,

7

41

0

C

/

T

U

P

C

4

t

i

B-

X

k

c

a

b

d

a

e

R

4

S

F

3

t

i

B-

X

k

c

a

b

d

a

e

R

3

S

F

2

t

i

B-

X

k

c

a

b

d

a

e

R

2

S

F

1

t

i

B-

X

k

c

a

b

d

a

e

R

1

S

F

0

t

i

B-

X

k

c

a

b

d

a

e

R

0

S

F

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B-

X

d

e

v

r

e

s

e

R

6

t

i

B-

X

d

e

v

r

e

s

e

R

5

t

i

B0

21

1

_

6

6

V

3

4

t

i

B1

31

K

L

C

_

H

C

V

/

0

_

6

6

V

3

3

t

i

B-

X

d

e

v

r

e

s

e

R

2

t

i

B-

X

d

e

v

r

e

s

e

R

1

t

i

B2

21

3

_

6

6

V

3

0

t

i

B1

21

2

_

6

6

V

3

t

i

B#

n

i

PD

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B-

X

)

k

c

a

b

d

a

e

R

(

L

E

S

T

L

U

M

6

t

i

B7

11

6

_

K

L

C

I

C

P

5

t

i

B6

11

5

_

K

L

C

I

C

P

4

t

i

B5

11

4

_

K

L

C

I

C

P

3

t

i

B2

11

3

_

K

L

C

I

C

P

2

t

i

B1

11

2

_

K

L

C

I

C

P

1

t

i

B0

11

1

_

K

L

C

I

C

P

0

t

i

B9

1

0

_

K

L

C

I

C

P

Notes:

1. PWD = Power on Default

2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at

high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.

Bit

Pin#

PWD

Description

Bit7

34

1

48MHZ_DOT

Bit6

35

1

48MHz_USB

Bit5

-

1

Reset gear shift detect 1 = Enable, 0 = Disable

Bit4

-

X

Reserved

Bit3

31

0

3V66_0/VCH_CLK, (default) = 66.66MHz, 1=48MHz

Bit2

-

X

Reserved

Bit1

6

1

PCICLK8

Bit0

5

1

PCICLK7