LMV921 datasheet(19/42 Pages) NSC

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2-13

LMV921 Qualification Package

2.0 DEVICE INFORMATION

Application Note

1.0 Unity Gain Pulse Response Considerations

The unity-gain follower is the most sensitive configuration to

capacitive loading. The LMV921 can directly drive 1nF in a

unity-gain with minimal ringing. Direct capacitive loading re-

duces the phase margin of the amplifier. The combination of

the amplifier’s output impedance and the capacitive load in-

duces phase lag. This results in either an underdamped

pulse response or oscillation. The pulse response can be im-

proved by adding a pull up resistor as shown in

Figure 1

Higher capacitances can be driven by decreasing the value

of the pull-up resistor, but its value shouldn’t be reduced be-

yond the sinking capability of the part. An alternate approach

is to use an isolation resistor as illustrated in

Figure 2.

2.0 Input Bias Current Consideration

The LMV921 has a bipolar input stage. The typical input bias

current (I

B) is 12nA. The input bias current can develop a sig-

nificant offset voltage. This offset is primarily due to I

B flow-

ing through the negative feedback resistor, R

F. For example,

if I

B is 50nA (max room) and RF is 100kΩ, then an offset volt-

age of 5mV will develop (V

OS = IBXRF). Using a compensa-

tion resistor (R

C), as shown in Figure 3, cancels this affect.

But the input offset current (I

OS) will still contribute to an off-

set voltage in the same manner.

3.0 Operating Supply Voltage

The LMV921 is guaranteed to operate from 1.8V to 5.0V.

The LMV921 will begin to function at power voltages as low

as 1.2V at room temperature when unloaded. Start up volt-

age increases to 1.5V when the amplifier is fully loaded

(600

Ω to mid-supply). Below 1.2V the output voltage is not

guaranteed to follow the input.

Figure 4 below shows the out-

put voltage vs. supply voltage with the LMV921 configured

as a voltage follower at room temperature.

4.0 Input and Output Stage

The rail-to-rail input stage of LMV921 provides more flexibil-

ity for the designer. The LMV921 uses a complimentary PNP

and NPN input stage in which the PNP stage senses com-

mon mode voltage near V

− and the NPN stage senses com-

mon mode voltage near V

+. The transition from the PNP

stage to NPN stage occurs 1V below V

+. Since both input

stages have their own offset voltage, the offset of the ampli-

fier becomes a function of the input common mode voltage

and has a crossover point at 1V below V

+ as shown in the

OS vs. VCM curves.

DS100979-41

FIGURE 1. Using a Pull-Up Resistor at the Output for

Stabilizing Capacitive Loads

DS100979-43

FIGURE 2. Using an Isolation Resistor to Drive Heavy

Capacitive Loads

DS100979-59

FIGURE 3. Canceling the Voltage Offset Effect of Input

Bias Current

DS100979-D2

FIGURE 4.

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