LM4550 datasheet(16/25 Pages) NSC

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Application Information

AC Link Serial Interface Protocol

AC Link Output Frame: SDATA_OUT (output from

controller, input to LM4550)

The audio output frame (output from AC ’97 Controller)

contains control and PCM data targeted for the LM4550

control registers and stereo DAC. The Tag slot, slot 0, con-

tains 16 bits that tell the AC Link interface circuitry on the

LM4550 the validity of the following data slots.

A new audio output frame is signaled with a low to high

transition of SYNC. SYNC is synchronous to the rising edge

of BIT_CLK. On the next rising edge of BIT_CLK, the AC ’97

Controller drives SDATA_OUT with the first bit of slot 0. The

LM4550 samples SDATA_OUT on the falling edge of BIT-

_CLK. The AC ’97 Controller will continue outputting the

SDATA_OUT stream on each successive rising edge of

BIT_CLK.

SDATA_OUT Slot 0: Tag Phase

The first bit of slot 0 is designated the "Valid Frame" bit. If this

bit is 1, it indicates that the current data frame contains at

least one slot of valid data and the LM4550 will further

sample the next four bits and slots7&8and6&9to

determine which frames do in fact have valid data. Valid slots

are signified bya1in their respective slot bit position.

10097204

FIGURE 3. AC 97 Bidirectional Audio Frame

10097206

FIGURE 4. AC Link Audio Output Frame

10097205

FIGURE 5. Start of Audio Output Frame

LM4550 데이터시트(PDF) 16 Page - National Semiconductor (TI)