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WM8281ECS/R 데이터시트(PDF) 258 Page - Cirrus Logic |
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WM8281ECS/R 데이터시트(HTML) 258 Page - Cirrus Logic |
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258 / 392 page ![]() WM8281 258 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 9 SYSCLK_ENA_L OW_STS 0 SYSCLK_ENA Status 0 = SYSCLK_ENA is enabled 1 = SYSCLK_ENA is disabled When a ‘0’ is written to SYSCLK_ENA, then no other control register writes should be attempted until SYSCLK_ENA_LOW_STS=1. 8 ISRC1_CFG_ER R_STS 0 ISRC1 Configuration Error Interrupt 0 = Normal 1 = Configuration Error 7 ISRC2_CFG_ER R_STS 0 ISRC2 Configuration Error Interrupt 0 = Normal 1 = Configuration Error 6 ISRC3_CFG_ER R_STS 0 ISRC3 Configuration Error Interrupt 0 = Normal 1 = Configuration Error 5 HP3R_DONE_ST S 0 HPOUT3R Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) 4 HP3L_DONE_ST S 0 HPOUT3L Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) 3 HP2R_DONE_ST S 0 HPOUT2R Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) 2 HP2L_DONE_ST S 0 HPOUT2L Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) 1 HP1R_DONE_ST S 0 HPOUT1R Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) 0 HP1L_DONE_ST S 0 HPOUT1L Enable Status 0 = Busy (sequence in progress) 1 = Idle (sequence completed) R3363 (0D23h) Interrupt Raw Status 4 8 BOOT_DONE_S TS 0 Boot Status 0 = Busy (boot sequence in progress) 1 = Idle (boot sequence completed) Control register writes should not be attempted until Boot Sequence has completed. 5 ADC_OVERFLO W_STS 0 ADC Overflow Status 0 = Normal 1 = ADC Overflow 4 ADC_FIFO_OU_ STS 0 ADC FIFO Status 0 = Normal 1 = ADC FIFO Error 3 ASRC_CFG_ER R_STS 0 ASRC Configuration Error Interrupt 0 = Normal 1 = Configuration Error 1 FLL2_CLOCK_O K_STS 0 FLL2 Clock OK Interrupt 0 = FLL2 Clock is not OK 1 = FLL2 Clock is OK 0 FLL1_CLOCK_O K_STS 0 FLL1 Clock OK Interrupt 0 = FLL1 Clock is not OK 1 = FLL1 Clock is OK R3364 (0D24h) 13 PWM_OVERCLO CKED_STS 0 Indicates an Overclocked Error condition for each respective sub-system. |
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