전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

WM8281ECS/R 데이터시트(PDF) 273 Page - Cirrus Logic

부품명 WM8281ECS/R
상세설명  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R 데이터시트(HTML) 273 Page - Cirrus Logic

Back Button WM8281ECS/R Datasheet HTML 269Page - Cirrus Logic WM8281ECS/R Datasheet HTML 270Page - Cirrus Logic WM8281ECS/R Datasheet HTML 271Page - Cirrus Logic WM8281ECS/R Datasheet HTML 272Page - Cirrus Logic WM8281ECS/R Datasheet HTML 273Page - Cirrus Logic WM8281ECS/R Datasheet HTML 274Page - Cirrus Logic WM8281ECS/R Datasheet HTML 275Page - Cirrus Logic WM8281ECS/R Datasheet HTML 276Page - Cirrus Logic WM8281ECS/R Datasheet HTML 277Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 273 / 392 page
background image
WM8281
Rev 4.0
273
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R340
(0154h)
Rate
Estimator
3
4:0
SAMPLE_RATE_
DETECT_B [4:0]
00h
Automatic Detection Sample Rate B
(Up to four different sample rates can be
configured for automatic detection.)
Register coding is same as
SAMPLE_RATE_n.
R341
(0155h)
Rate
Estimator
4
4:0
SAMPLE_RATE_
DETECT_C [4:0]
00h
Automatic Detection Sample Rate C
(Up to four different sample rates can be
configured for automatic detection.)
Register coding is same as
SAMPLE_RATE_n.
R342
(0156h)
Rate
Estimator
5
4:0
SAMPLE_RATE_
DETECT_D [4:0]
00h
Automatic Detection Sample Rate D
(Up to four different sample rates can be
configured for automatic detection.)
Register coding is same as
SAMPLE_RATE_n.
R3104
(0C20h)
Misc Pad
Ctrl 1
13
MCLK2_PD
0
MCLK2 Pull-Down Control
0 = Disabled
1 = Enabled
R3105
(0C21h)
Misc Pad
Ctrl 2
12
MCLK1_PD
0
MCLK1 Pull-Down Control
0 = Disabled
1 = Enabled
Table 101 Clocking Control
In AIF Slave modes, it is important to ensure the applicable clock domain (SYSCLK or ASYNCCLK) is
synchronised with the associated external LRCLK. This can be achieved by selecting an MCLK input
that is derived from the same reference as the LRCLK, or can be achieved by selecting the external
BCLK or LRCLK signal as a reference input to one of the FLLs, as a source for SYSCLK or
ASYNCCLK.
If the AIF clock domain is not synchronised with the LRCLK, then clicks arising from dropped or
repeated audio samples will occur, due to the inherent tolerances of multiple, asynchronous, system
clocks. See “Applications Information” for further details on valid clocking configurations.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com