 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
WM8281ECS/R 데이터시트(PDF) 387 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
WM8281ECS/R 데이터시트(HTML) 387 Page - Cirrus Logic |
|
|
387 / 392 page  WM8281 Rev 4.0 387 In each case, the SYSCLK (ASYNCCLK) frequency must be a valid ratio to the LRCLK frequency; the supported clocking rates are defined by the SYSCLK_FREQ (ASYNC_CLK_FREQ) and SAMPLE_RATE_n (ASYNC_SAMPLE_RATE_n) registers. The valid AIF clocking configurations are illustrated in Figure 95 to Figure 101 below. Note that, where MCLK1 is illustrated as the clock source, it is equally possible to select MCLK2 as the clock source. Similarly, in cases where FLL1 is illustrated, it is equally possible to select FLL2. AIFn (Master Mode) Oscillator WM8281 Processor AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT SYSCLK (or ASYNCCLK) SYSCLK_SRC (or ASYNCCLK_SRC) Figure 95 AIF Master Mode, using MCLK as Reference Oscillator WM8281 AIFn (Master Mode) Processor AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT FLL1_REFCLK_SRC FLL1 SYSCLK (or ASYNCCLK) SYSCLK_SRC (or ASYNCCLK_SRC) Figure 96 AIF Master Mode, using MCLK and FLL as Reference |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
