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HD3SS460RNHT 데이터시트(PDF) 16 Page - Texas Instruments |
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HD3SS460RNHT 데이터시트(HTML) 16 Page - Texas Instruments |
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16 / 37 page ![]() HD3SS460 ML0+ ML0> ML1+ ML1> ML2+ ML2> ML3+ ML3> RX1+ RX1> TX1+ TX1> TX2+ TX2> RX2+ RX2> DP Sink SSTX SSRX Vcm > 2.0 V 0.1 µF 0.1 µF 500 nF 500 nF 100 lQ 100 lQ 100 lQ 100 lQ Copyright © 2016, Texas Instruments Incorporated 16 HD3SS460 SLLSEM7D – JANUARY 2015 – REVISED JANUARY 2017 www.ti.com Product Folder Links: HD3SS460 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated USB SS and DP as Alternate Mode (continued) Figure 6. HD3SS460 USB Upstream (DP Sink Implementation Example) 9.2.1 Design Requirements DESIGN PARAMETERS EXAMPLE VALUES VCC 3.3 V Decoupling capacitors 0.1 µF AC Capacitors 75-200nF (100nF shown) USBSS TX p and n lines require AC capacotprs. Alternate mode signals may or may not require AC capacitors Control pins Controls pins can be dynamically controlled or pin-strapped. The POL signal is controlled by CC logic in the Type-C ecosystem. |
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