The parallel port supports Centronics type printers. When CS2* is low, the parallel port is selected allowing access to all

parallel port data, control and status registers.

PARALLEL PORT REGISTER ADDRESSES

Cs2*

A1

A0

IOR*

LOW*

Operation

0

0

0

0

0

0

0

0

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

Read Port Data Register

Read Port Status Register

Read Port Control Register

Invalid Operation

Write Port Data Register

Invalid Operation

Write Port Control Register

Invalid Operation

ACCESSIBLE PARALLEL PORT REGISTERS

Bit

No

.

Port

Data

Register

Port

Status

Register

(Read

only)

Port

Control

Registe

r

0

1

2

3

4

5

6

7

Data Bit 0

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

1

1

1

ERRORS*

SLCTS

PES

ACKS*

BUSYS*

STBE

AFDE

INITE*

SLINE

INTE

1

1

1

Register

Description

Port Data Register

This 8-bit data register can be modified by the

CPU to write data to the parallel port.

Bits 0-7:

Data bits

Port Status Register

This register is a read only register reporting

the state of status input pins ERROR*, SLCT,

PE, ACK*, and BUSY.

Bits 0:2:

these bits are always read as 1.

Bits 3:

Reports status of ERROR* pin.

Bits 4:

Reports status of SLCT pin.

Bits 5:

Reports status of PE pin.

Bits 6: Reports status of ACK*.

Bits 7: Reports inverted status of BUSY pin.

Port Control Register

This register controls

output pins STB*,

AFD*, INIT*, SLIN*, INT2, When read, it

reports the status of the control pins.

Bits 0: This bit, when written 1/0, force STB*

pin low/high.

Bits 1: This bit, when written 1/0, force AFD*

pin low/high.

Bits 2: This bit, when written 1/0, force INIT*

pin low/high.

Bits 3: This bit, when written 1/0, force SLIN*

pin low/high.

Bits 4: This bit, when written 1/0, enables /

disables INT2 pin.

Bits 5-7: Always read as 1.

21

408-432-9100/www.impweb.com

© 2002 IMP, Inc.

Parallel Port Description

IMP16C552

IMP16C552