INTEL82801 datasheet(89/414 Pages) INTEL

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82801AA and 82801AB Datasheet

5-39

Functional Description

5.9.5

Data Frame Format

Table 5-25 shows the format of the data frames. For the PCI interrupts (A-D), the output from the

ICH is ANDed with the PCI input signal. This way, the interrupt can be signaled via both the PCI

interrupt input signal and via the SERIRQ signal (they are shared).

Table 5-25. Data Frame Format

Data

Frame #

Interrupt

Clocks Past

Start Frame

Comment

IRQ0

Ignored. IRQ0 can only be generated via the internal 8524

2IRQ1

SMI#

Causes SMI# if low. Sets SERIRQ_SMI_STS status bit.

4IRQ3

5IRQ4

6IRQ5

7IRQ6

8IRQ7

IRQ8

Ignored. IRQ8# can only be generated internally or on ISA.

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

Ignored. IRQ13 can only be generated from FERR#

IRQ14

Do not include in BM IDE interrupt logic

IRQ15

Do not include in BM IDE interrupt logic

IOCHCK#

Same as ISA IOCHCK# going active.

PCI INTA#

Drive PIRQA#

PCI INTB#

Drive PIRQB#

PCI INTC#

Drive PIRQC#

PCI INTD#

Drive PIRQD#

INTEL82801 데이터시트(PDF) 89 Page - Intel Corporation

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