| 전자부품 데이터시트 검색엔진 |
|
DG183AP/883 데이터시트(PDF) 8 Page - TEMIC Semiconductors |
|
|
|||||||||||||||||||||||||||||
DG183AP/883 데이터시트(HTML) 8 Page - TEMIC Semiconductors |
|
8 / 8 page ![]() DG183/184/185 8 Siliconix S-52895—Rev. D, 16-Jun-97 Test Circuits Feedthrough due to charge injection may result in spikes at the leading and trailing edge of the output waveform. Figure 2. Switching Time Logic Input Switch Output tOFF tON tr <10 ns tf <10 ns 90% 50% 0 V 3 V 0 V 0 V 90% 3 V –3 V tON: VS = 3 V tOFF:VS = –3 V V OUT + VS x R L R L ) rDS(on) –15 V GND IN CL (includes fixture and stray capacitance) V– D1 VO1 S2 S1 D2 RL2 CL2 VO2 RL1 CL1 VS2 VS1 +15 V V+ +5 V VL Application Hintsa Switch V+ Positive Supply Voltage (V) V– Negative Supply Voltage (V) VL Logic Supply Voltage (V) VR Reference Supply Voltage (V) VIN Logic Input Voltage VINH(min)/VINL(max) (V) VS Analog Voltage Range (V) DG183 DG184 15b 10 12 –15 –20 –12 5 5 5 GND GND GND 2.0/0.8 2.0/0.8 2.0/0.8 –7.5 to 15 –12.5 to 10 –4.5 to 12 DG185 15b 10 12 –15 –20 –12 5 5 5 GND GND GND 2.0/0.8 2.0/0.8 2.0/0.8 –10 to 15 –15 to 10 –7 to 12 Notes: a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing. b. Electrical Parameter Chart based on V+ = 15 V, VL = 5 V, VR = GND. |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |