AC Electrical Characteristics

FPD-Link INPUT TIMING V

Symbol

Parameter

Conditions

Min

Typ

Max

Units

RPLLS

FPD-Link Receiver Phase Lock

Loop Wake-up Time

10

ms

RSKM

RxIN Skew Margin (Note 4)

V

400

ps

Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs.

This margin takes into account transmitter output skew (TCCS) and the setup and hold time (internal data sampling window) allowing for FPD-Link LVDS cable skew

dependent on type/length of cable, and source clock (FPD-Link Transmitter TxCLK IN) jitter.

RSKM

≤ cable skew (type, length) + source clock jitter (cycle to cycle). The specified RSKM minimum assumes a TPPOSmax limit of 200ps (65MHz). This parameter

is Guaranteed by Design.

DS101077-6

FIGURE 1. FPD87310 Input I

DS101077-7

SW

Setup and Hold Time (internal data sampling window)

TCCS

Transmitter Output Skew

RSKM

≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)

Cable Skew Typically 10 ps - 40 ps per foot.

FIGURE 2. FPD87310 (FPD-Link Receiver) Input Skew Margin

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