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LM4930 데이터시트(PDF) 11 Page - National Semiconductor (TI)

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부품명 LM4930
상세설명  Audio Subsystem with Stereo Headphone & Mono Speaker Amplifiers
PDF  33 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM4930 데이터시트(HTML) 11 Page - National Semiconductor (TI)

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Electrical Characteristics DV
DD = 3.3V, AVDD = 5V, RLHP =32Ω,RLHF =8Ω
(Notes 1, 2, 8) (Continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for T
A= 25˚C.
Symbol
Parameter
Conditions
LM4930
Units
(Limits)
Typical
(Note 6)
Limits
(Notes 7,
15)
LPB
VADC
Voice ADC Lower Passband
Cutoff Frequency.
Lower -3dB Point
0.230
kHz
SBA
VADC
Voice ADC Stopband Attenuation
Above 4kHz
65
dB
SBA
NOTCH Voice ADC Notch Attenuation
Centered on 55Hz, figure gives worst
case attenuation for 50Hz & 60Hz.
58
dB
R
DAC
Audio DAC Ripple
20Hz - 20kHz through head-phone output.
+/-0.1
+/-0.2
dB (max)
PB
DAC
Audio DAC Passband Width
-3dB point
22.7
kHz
SBA
DAC
Audio DAC Stopband Attenuation
Above 24kHz
76
dB
DR
DAC
Audio DAC Dynamic Range
Digital Filter Section
Signal = VO at f = 1kHz @ 1% THD+N;
f = 1kHz; Noise for -60dBFS digital input;
0dB gain; A-weighted
97
dB
SNR
DAC
Audio DAC SNR Digital Filter
Section
Signal = VO at f = 1kHz @ 1% THD+N;
f = 1kHz; Noise for -60dBFS digital input;
0dB gain; A-weighted
97
dB
∆A
CH-CH
Stereo Channel-to-Channel Gain
Mismatch
0.3
dB
V
IL
Digital Input: Logic Low Voltage
Level
0.4
V
V
IH
Digital Input: Logic High Voltage
Level
1.4
V
Volume Control Range
(Headphone amplifiers)
Maximum Attenuation
Minimum Attenuation
-46.5
0
dB
dB
Volume Control Range (Mono
speaker amplifier)
Minimum Gain
Maximum Gain
-34.5
12
dB
dB
Volume Control Step Size (Output
amplifiers)
1.5
dB
Volume Control Range
(Microphone Preamp)
Minimum Gain
Maximum Gain
17
47
dB
dB
Volume Control Step Size
(Microphone Preamp)
2dB
Side Tone Attenuation Range
Maximum Attenuation
Minimum Attenuation
-30
0
dB
dB
Side Tone Attenuation Step Size
3
dB
f
MCLK
MCLK frequency
CLOCK_DIV = 0
CLOCK_DIV = 1
12.288
24.576
MHz
MHz
MCLK Duty Cycle
50
40
60
% (min)
% (max)
f
CONV
Sampling Clock Frequency (Note
9)
48
kHz
f
CLKSCL
SCL_CLK Frequency
400
kHz
t
RISESCL
SCL_CLK, SCL_DATA Rise Time
300
ns
t
FALLSCL
SCL_CLK, SDA_DATA Fall Time
300
ns
t
SDAH
SDA_DATA Hold Time
500
ns
t
SDAS
SDA_DATA Setup Time
500
ns
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