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7903A – AVR – 2006/02

The AVR features three main levels of clock gating.

Figure 3: Three main levels of clock gating

Clock Gating Level One: Sleep Functionality

The first level of clock gating are the sleep modes that have always existed on the AVR.

The sleep modes gate the clock distribution to a group of functionality thereby enabling

different levels of sleep and functionality.

•

Idle mode gates the CPU clock domain and the Flash clock domain while the

peripherals and interrupt system continue to operate.

•

The ADC noise reduction mode allows the ADC to operate while most of the peripheral

clock domains, in addition to the CPU clock domain, and the Flash clock domain are

gated.

•

The Power Down mode gates all clock domains on the AVR and only enabled

asynchronous operation is allowed. The external oscillator is also stopped in Power

Down mode.

•

The Power Save mode is the same as Power Down mode except that the

asynchronous timer can operate when it is enabled.

•

The Standby mode is the same as Power Down mode except that the main oscillator is

kept running.