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34C60 데이터시트(PDF) 39 Page - SMSC Corporation

부품명 34C60
상세설명  PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE
PDF  58 Pages
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제조업체  SMSC [SMSC Corporation]
홈페이지  http://www.smsc.com
Logo SMSC - SMSC Corporation

34C60 데이터시트(HTML) 39 Page - SMSC Corporation

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SMSC DS – PPC34C60
Page 39
Rev. 06/01/2001
ADVANCED INFORMATION
FIGURE 12 - SPP DATA WRITE TIMING (PARALLEL PORT SIGNALS
)
This signaling sequence pertains to a device that has been previously selected to communicate via SPP Mode.
SPP DATA WRITE TIMING (PARALLEL PORT SIGNALS)
PARAMETER
MIN
TYP
MAX
UNITS
t1
nINIT controls the direction of the parallel
port when in SPP mode. nINIT deasserted
to HD[0:7] released to high impedance by
the PPC34C60.
84
[2 SCLK]
125
[3 SCLK]
ns
t2
Valid data on HD[0:7] to nSTB asserted
edge.
125
[3 SCLK]
ns
t3
BSY deasserted (low) to nSTB asserted
edge.
0
ns
t4
nSTB asserted pulse width.
125
[3 SCLK]
ns
t5
Valid data hold from nSTB deasserted
edge.
125
[3 SCLK]
ns
t6
nSTB asserted edge to BSY asserted
edge.
333
[8 SCLK]
375
[9 SCLK]
ns
t7
BSY asserted pulse width. These values
are based on BCLK = 2 SCLK.
0
1,084
[13 BCLK]
ns
t1
t5
t5
t2
t3
t4
t2
t3
t4
t6
t7
t6
HD[0:7]
nSTB H
nALF H
nSEL H
nINIT H
BSY P
nACK P
PE P
SLCT P
nERR P



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